China’s domestic semiconductor industry landscape has changed considerably. The Biden administration has continued to impose export control restrictions on Chinese firms, and the October 7, 2022, package of controls targeted not only advanced semiconductors (such as GPUs used for running artificial intelligence and machine learning workloads) but also expanded significantly on controls over semiconductor manufacturing equipment (SME). One goal of the U.S. controls is to prevent Chinese firms from moving into nonplanar technology processes, such as FinFET and eventually Gate All Around (GAA). The new restrictions included novel end-use controls and controls on U.S. persons, posing major new challenges...
More efficient chips do not have emergent behaviours (outside of, say, mobile and autonomous vehicles). More efficient chips make things more economical. Total compute capability is a function of manufacturing capability (which reflects in capital cost), electricity (which reflects in operating cost), and efficiency (which also reflects in operating cost). If your manufacturing capability is obscene and your electricity output is obscene, then you can handwave a lot of efficiency concerns by just scaling the number of chips you have in a system. In terms of aggregate computing capability, 5nm is more than sufficient to keep pace given enough scale.
There’s an interesting figure that I saw a while ago: China’s % of electricity generation dedicated to data centers is lower than both the US and EU, and due to top line electricity generation growth this proportion is basically not expected to move in the next decade. China has a LOT of freedom to tank efficiency losses that other regions simply do not.
There’s a small condition here that scaling usually has some degree of losses, but for LLM training it’s basically non-existent and for supercomputing it’s supposed to be around 10% losses due to networking/etc.
More efficient chips do not have emergent behaviours (outside of, say, mobile and autonomous vehicles). More efficient chips make things more economical. Total compute capability is a function of manufacturing capability (which reflects in capital cost), electricity (which reflects in operating cost), and efficiency (which also reflects in operating cost). If your manufacturing capability is obscene and your electricity output is obscene, then you can handwave a lot of efficiency concerns by just scaling the number of chips you have in a system. In terms of aggregate computing capability, 5nm is more than sufficient to keep pace given enough scale.
There’s an interesting figure that I saw a while ago: China’s % of electricity generation dedicated to data centers is lower than both the US and EU, and due to top line electricity generation growth this proportion is basically not expected to move in the next decade. China has a LOT of freedom to tank efficiency losses that other regions simply do not.
There’s a small condition here that scaling usually has some degree of losses, but for LLM training it’s basically non-existent and for supercomputing it’s supposed to be around 10% losses due to networking/etc.
That is interesting, do you recall where you saw that data about electricity generation growth in different countries?